CS 395T: Fine-grained parallelism

Spring 2006
Unique ID: 54212

Time: Th 3:30-6:15. Location: BEN 1.124

Professor: Bill Mark billmark@cs.utexas.edu

Office Hours: Friday 5pm-6pm or by appointment

Basic Information

Final project

Seminar topic

Single-chip multiprocessor architectures provide the opportunity to exploit fine-grained thread-level parallelism. By 'fine-grained parallelism' we are referring to threads that execute 10-500 instructions before termination or the next inter-thread communication/synchronization. We are explicitly *not* referring to instruction level parallelism within a single thread.

Exploiting fine-grained parallelism requires support from the hardware architecture, the programming language and the runtime system. Applications must also be explicitly designed to expose this form of parallelism. We will read papers from the architecture literature , programming language literature, and algorithm/application literature that provide insight into how to exploit fine-grained parallelism in future systems.

Seminar methodology

This course will be a seminar-style course. Most class periods will consist of one or more paper presentations by students in the class, followed by group discussion and brainstorming about the topics discussed in the papers. The presentations of papers will be expected to contain throughtful analysis of the papers rather than just rote regurgitation. Students will be expected to read the assigned papers before each class, since the the goal is to use the class time for creative dicussions.


If you have any questions, feel free to contact me (Bill Mark) by email.
(c) 2005-2006 Bill Mark