Frontiers in Computer Architecture, May 1, 2007
==================================

Diagram:

APP - COMPILER - uARCH - VLSI Technology

past: circle around VLSI, uARCH, a bit of compiler
future: circle around app, compiler, a bit of uarch.
trips: circle around a bit of app, complier, uarch, a bit of VLSI


Goals
-----
* Performance
* Low cost
* Security
* Low power
* Ease of programming
* Compatibility, etc.
* Reliability


Our focus has been on performance.
In the future, security will be more important in many cases.
So will power.

World for architects:
---------------------
Manycore:
  * look at ops/W and ops/mm^2, not absolute ops as in the past
  * focus on interconnect and memory system, as well as mem/comm primitives
    the "uncore"
Specialization:
  * e.g. TCP/IP offload - requires domain knowledge to build these
Managed code:
  * efficient support for JIT compilers; and for correctness checks
    such as bounds checking.
    Java/.NET languages... e.g. deeper calling stacks
Device reliability:
  * What kind of redundancy?

World for software
------------------
If you care about performance or power consumption, need to understand
parallelism and caches, probably multithreading too.
New kind of SW person:
   - parallel high-performance library/framework writer
   * arch focus on caches, interconnect, etc.
   * SW focus on parallelism and memory locality


BACKUP MATERIAL
==============

Architecture can mean two things
--------------------------------
* HW/SW interface -- classical definition of architecture
* Microarchitecture -- pipelining, branch prediction, caches, ...

Trends
------
* Power consumption is now a first-order constraint
   - on desktops
   - definitely for mobile computing -- Laptops, PDAs, smart watches
* We are reaching limits of instruction-level parallelism
* Increasing use of virtual machines (Java, .NET, DX9 shaders)
  [aka 'managed code']
    - the most important interfaces is the bytecode, not the HW arch
    - frequent use of dynamic memory allocation
    - reasons: 

Trends
------
* Specialization
    . on a chip - TCP/IP offload, etc.
    . different markets
    . Examples: server (Azul, Niagara); desktop; ultra-mobile; cellphone;
		game console/graphics; ...
* Parallelism, even on chip
    . Why:
       . only route to peak performance
       . better power efficiency
       . lower cost (via better yield using floorsweeping)
    . Leads to:
       . change in programming model
       . focus on interconnect and memory system, not core
       . user-level architecture changes to support communication and
         synchronization
* Architectural support for JIT/managed code
    . garbage collection
    . multithreading
    . secure code
    . etc.

* Power efficiency
    . this is highly microarchitectural
    . device properties; voltages; transistor sizes; pipeline depths; etc.
    . clock gating, etc.
    
* Dealing with device unreliability
* Dealing with device variability

AS AN ARCHITECT
---------------
* System layers are breaking down:
  . Learn more about power
  . Learn more about applications (for parallelism)
  . Learn more about parallelism primitives

AS A PROGRAMMER
---------------
* Learn more about parallelism
* Learn more about managed code