Lecture #19 -- Review for Exam #2 ================================= Don't forget ------------ * Calculator -- NOT cell phone or PDA or computer * Book * Appendix A * Pencil Basic rules ----------- * Open book - bring your copy of Appendix A from last time!!! * Open lecture notes (in printed form) * Your *own* study notes (notes assembled in small group OK). * Your *own* homeworks & our solutions & your own exam #1 & our solutions * No other materials * Calculator (used in non-programmable mode). You cannot use cell phone, computer, etc. as calculator. * No cell phones or other wireless devices anywhere. * No computers. How to study ------------ * We try to test for understanding, not regurgitation. Studying accordingly will help. * The test is timed; you won't have enough time to learn everything 'from the book' during the exam. Your goal should be to only the book as an occasional reference during the exam for specific details. * Do you understand every homework problem and why? * Do you understand everything in the chapters we read and the lectures notes? * Do you understand *why* formulas work the way they do? Do you understand *why* pipelines and caches are designed the way they are? * Can you *apply* the material to new problems? . Do any homework problems that you skipped before. . Do additional homework problems. ('for more practice' problems have solutions on CD) What will be covered? -------------------- - All material from previous exam, but emphasis will be on new material: Lectures #8-18 P&H Ch 5, 6, 7.1-7.3 (caches) HW's #3, 4, 5 See schedule on web page. Lectures notes are also on web page. Especially important review topics ---------------------------------- * Performance measurement and modelling: - CPI - execution time - speedup New Topics ---------- * Processor datapth . instruction fetch, instruction decode, register file, ALU, etc. . HW diagrams in book * Control of the processor datapath . how all of the mux's get set * Multicycle machine * Pipelined machine . basic structure - 5 stages; latches between stages . hazards -- data, control, and structural . forwarding/bypassing as a fix for data hazards . branch prediction as a fix for control hazards * Multiple-issue machines (at a superficial level) * Caches . Why they work - spatial and temporal locality . Average memory access time (AMAT) . Basic cache choices: direct-mapped, fully associative, set-associative . How addresses are mapped to locations in the cache . Replacement policies for associative caches . Policies on writing: Write back vs. write thru . Policies on write misses: Write allocate vs no-write-allocate . How changes to different cache configuration parameters can effect performance, and why . Multi-level cache hierarchies, and AMAT for them What kinds of problems might we have? (non-inclusive list) ---------------------------------------------------------- * Performance/speedup analysis and comparison * For a particular pipelined machine and instruction sequence, identify all of the data hazards and/or pipeline bubbles. * For a somewhat different pipeline than the one in the book, identify all of the forwarding paths. [idea is to test if you really understand how forwarding/bypassing works] * Describe performance gain/loss from correct or incorrect branch prediction * Given a hardware diagram, show the changes necessary to add a simple new capability * Be a human cache controller -- show cache contents after a particular sequences of memory requests * Compute change in number of blocks if block size is changed while holding cache size constant. * For a particular piece of code or memory access pattern, specify the optimal cache design (e.g. block size). * Compute AMAT for a multi-level cache hierarchy * At least one hard/creative problem