Lecture 07, part II:
Introduction to implementation of the MIPS architecture
=======================================================
(These are quick notes used to guide the blackboard portion of the lecture)

In designing a CPU implementation (or anything else for that matter),
we need to know two things up front:
1) What does the CPU need to do?
   (i.e. what steps would be required to complete each instruction in the ISA)
2) What parts are available to us?

WHAT DOES THE CPU NEED TO DO
============================

For MIPS, there are three major categories of instructions:
A) ALU -- e.g. XOR R2, R3, R4

B) Load/Store -- e.g. LW R2, 0x300(R3)
                 e.g. SW R4, 0x200(R5)
C) Branch/Jump -- e.g. BEQ R7, R8, Blah
		  e.g. J Blah

We can break the execution of any of these instructions into six stages: (explain each one)
a) Instruction Fetch
b) Instruction Decode
c) Read from registers
d) Execute
e) Memory read/write
f) Write to registers


Make a table:
                              ALU   || Load | Store || Branch | Jump
a) Instruction Fetch                ||              ||
b) Instruction Decode               ||              ||
c) Read from registers          etc.
d) Execute
e) Memory read/write
f) Write to registers

and fill it in, working on one type of instruction at a time.
Before starting to work on the instruction,
write down its encoding as taken from Appendix A.


WHAT PARTS ARE AVAILABLE TO US?
===============================
Two categories:
  - data storage ("sequential logic")
  - data manipulation ("combinatorial logic")

Show the slides from the next lecture that have the actual parts:
MUX, Adder, Register File, etc.